The invention relates to an integrated circuit (IC) comprising at least one analog circuit, at least one digital circuit and at least one signal path between the analog circuit and the digital circuit.
Such circuits are found in a number of applications. An example in the area of video processing is a so-called one-chip TV, which is an IC that performs all television-specific signal processing, both analog and digital. For reasons of design and test efficiency, design of such an IC runs along the lines of identifying a number of more or less independent subfunctions and implementing these subfunctions as separate circuits or functional blocks, also called cores or macros. In a later design stage, the various (analog and digital) macros are interconnected through a number of signal paths, thereby eventually enabling the IC to perform its intended functionality.
Production testing of such an IC is preferably carried out according to the macro test concept, i.e. all macros are tested individually, rather than that the IC is tested as a whole. For further information on macro testing reference is had to U.S. Pat. No. 5,477,548.
The presence of the signal path between the analog and the digital macro poses a number of problems when separately testing these macros. If the signal path establishes an input to the digital macro, for the test of the digital macro it represents an uncontrollable input, whereas for the test of the analog macro, the signal path forms an unobservable output. Similar problems occur when the signal path establishes an input to the analog macro.
A well known approach to enhance observability and controllability in a digital circuit is to use a scan-based design. In a scan-based design, the memory elements (e.g. flip-flops) are not only connected to each other via normal data paths, establishing the intended functionality of the circuit, but also via so-called scan data paths, which establish one or more so-called scan chains. A scan chain is essentially a shift register that allows the memory elements therein to be loaded and unloaded serially, in that way allowing the digital circuit to be tested according to the scan test principle. The scan test principle works as follows. Firstly, the digital circuit is put to a scan state, during which test patterns are shifted into the scan chains. Secondly, the digital circuit is put to an execution state, which results in response patterns being generated in the scan chains under influence of the loaded test patterns. Thirdly, after putting the digital circuit into the scan state again, the response patterns are shifted out from the scan chains for evaluation. This sequence can be repeated for a large number of test patterns and combinations of input signals. Faults result in deviating response patterns.
If the digital macro is intended to have a scan based design, the lack of controllability and observability of the signal path could be reduced by taking care that the signal path on the boundary of the digital circuit passes through a scannable memory element, i.e. through a memory element that is part of a scan chain. Again assuming that the signal path is an input to the digital macro, the scannable memory element provides an instrument for observing signals produced by the analog macro, and for controlling incoming signals to the digital macro. The same applies to the situation that the signal path provides an input to the analog macro. Such kind of configuration, however, offers only limited test opportunities for the analog and the digital macro.
It is an object of the invention to provide an IC as specified in the preamble which offers a broader range of test opportunities for testing the analog and the digital macro. To this end, the circuit according to the invention is characterized in that the signal path between the analog and the digital macro passes through a seam circuit via a seam input and a seam output thereof, the seam circuit comprising a feedback loop having a seam memory element being part of a scan chain and a seam multiplexer, the seam memory element feeding a first input of the multiplexer, a second input of the multiplexer representing the seam input, an output of the feedback loop representing the seam output. In this way, a first state of the multiplexer allows loading of a data bit into the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.
The seam circuit provides an observable and controllable node on the interface signal path between the digital and the analog macro. When the seam multiplexer is operated in the first state, an incoming signal at the seam input is presented to the input of the seam memory element so that it can be stored to be observed later on by appropriate shifting operations of the corresponding scan chain. Moreover, when the seam multiplexer is in the first state, the seam circuit is transparent or signals between the macros. When the seam multiplexer is operated in the second state, the outgoing signal at the seam output is determined by the value that is stored in the scannable memory element, which value can be loaded therein beforehand by appropriate shifting operations of the corresponding scan chain.
When the seam circuit is inserted in a signal path that provides an input to the digital macro, it further provides a way to really isolate the analog macro from the digital macro. This is particularly advantageous if the digital macro is to be tested by means of IDDQ testing. In IDDQ testing, use is made of the fact that a faultless CMOS IC draws a very low quiescent power-supply current (IDDQ). A number of faults, however, such as shorts, increase the power-supply current substantially if the IC is provided with appropriate test patterns activating the fault. By measuring the power-supply current to the digital macro, such faults can be detected. It is very important that while measuring the power-supply current, the digital macro is truly in a steady state. When, however, the signal path carries an asynchronous analog signal, that signal induces currents in the first stages of one or more memory elements, giving rise to a higher power-supply current, which conceals the faults to be detected. With the seam circuit in the signal path, this is avoided by putting the seam circuit in the second state. In the second state, the analog signal is disconnected from the digital macro and can no longer influence the IDDQ measurement, whereas the input of the memory element receives a well-defined signal from its own output. Thus, the seam circuit enables the digital macro to be tested by means of IDDQ as it provides a way to make the inputs to the digital macro stable. Moreover, the added seam circuit itself has a high test coverage.
Furthermore, when there is a plurality of signal paths between the macros, each of which signal paths being provided with a seam circuit, the fact that, in the second mode, the seam circuit output remains stable when the seam circuit is clocked, can be used advantageously when testing either one of the macros. This works as follows. By putting the seam circuits in signal paths that form outputs of the macro to be tested in the first state and the seam circuits in signal paths that form inputs to that macro in the second state, the outputs of the macro can be observed while the inputs are kept stable. This is particularly advantageous while testing the analog macro, if the analog macro through the signal paths receives control signals that are required for its proper setting. By keeping the input signals stable, disturbance of the analog macro is avoided. Such disturbance can better be avoided as it requires the analog macro to settle first before testing can proceed, thereby increasing total test time. Depending on the kind of analog macro and the kind of input signal, the settling time could be as high as 1 ms or even higher.
A first type of seam circuit is defined by the embodiment of the invention according to claim 2. The first type of seam circuit introduces a delay in the signal path that only comprises the delay of the multiplexer. A second type of seam circuit is defined by the embodiment of the invention according to claim 3. The second type of seam circuit is particularly advantageous in case a scannable flip-flop in the signal path is present anyway. Then the incorporation of the seam circuit hardly increases circuit area.
The embodiment of the invention according to claim 4 has the advantage that, while shifting in new test data/shifting out response data via the scan chain, the output of the seam circuit can be kept silent by means of the latch. This is particularly useful for signal paths providing an input to the analog macro. If to such an input a train of pulses would be presented, this could well cause disturbances in the analog macro, requiring some time for the analog macro to settle before testing can proceed after a shift operation. This wastes valuable test time.
The embodiment of the invention according to claim 5 has the advantage that the memory elements of the seam circuits can be read and written fast via the second scan chain, as the memory elements of the digital macro are in a way bypassed. Furthermore, the embodiment has the advantage that in the second test mode thereof it allows the digital macro to run in normal mode while simultaneously providing access to the seam memory elements via the second scan chain. This is particularly advantageous in case the analog macro requires dynamic input signals with a particular functional timing behaviour from the digital macro. By allowing the digital macro to run in normal mode, it can generate the dynamic input signals, whereas via the second scan chain other (static) input signals can be applied to the analog macro, and output signals of the analog macro can be sampled and accessed. A further advantage of the embodiment is that the analog macro can be tested even when the digital macro has faults, notably faults affecting the first scan chain. This is handy during the development process when first silicon is produced. Being able to determine whether or not the analog macro is faultless is already valuable information in that stage.
Non-prepublished International Application PCT/IB97/01346, corresponding to U.S. patent application Ser. No. 08/959782) describes an IC comprising a first and a second clock domain being respectively controlled by a first and a second clock signal, the first clock domain and the second clock domain being interconnected via a set of signal paths, each of which comprising a respective string of flip-flops, an initial flip-flop of the string being located in the first clock domain and a final flip-flop of the string being located in the second clock domain, the string being arranged for serially moving a data bit along its flip-flops from the first to the second clock domain under control of the first and the second clock signals. Each one of the signal paths includes a seam circuit comprising: a seam input; a seam output; a feedback loop having a seam multiplexer and a seam flip-flop being part of the relevant string and being part of a scan chain, the seam flip-flop feeding a first input of the multiplexer, a second input of the multiplexer representing the seam input, an output of the feedback loop representing the seam output; so that a first state of the multiplexer allows loading of a data bit into the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop. That PCT application does not disclose interconnected analog and digital circuits.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.